Murali Jayapala

Journal Papers

• Playing the Trade-Off Game Architecture Exploration Using COFFEE.
  Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar and Francky Catthoor. ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(3), May 2009. [BIB]
• Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
  Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi and Masaharu Imai. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, (to appear). [BIB]
• Distributed Loop Controller for Multi-threading in Uni-threaded ILP Architectures.
  Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor and Diederik Verkest. IEEE Transactions on Computers, 58(3):311-321, March 2009. [BIB]
• EMPIRE: Empirical Power/Area/Timing Models for Register Files.
  P.Raghavan, A.Lambrechts, M.Jayapala, F.Catthoor and D.Verkest. In Journal of Microprocessors and Microsystems, 2009. ((available online from Feb 20)). [BIB] [pdf]
• Interconnect-Exploration for Energy vs Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
  Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bengfeng Mei, Francky Catthoor and Diederik Verkest. IEEE Transactions on VLSI, 17(1):151-155, Jan 2009. [BIB]
• Locality Optimizations in a Compiler for Wireless Applications.
  Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala and Francky Catthoor. Design Automation of Embedded Systems (DAEM), April 2008. [BIB]
• Address Generation Optimization for Embedded High-Performance Processors: A Survey.
  Guillermo Talavera, Murali Jayapala, Jordi Carrabina and Francky Catthoor. Journal of Signal Processing Systems for Signal Image and Video Technology (formerly the Journal of VLSI Signal Processing Systems for Signal Image and Video Technology), 53(3):271-284, December 2008. [BIB]
• Efficient Method to Generate an Energy Efficient Schedule using Operation Shuffling.
  Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor and Masaharu Imai. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E91-A(2):604-612, Feb 2008. [BIB]
• Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
  Y. Kobayashi, M. Jayapala, P. Raghavan, F. Catthoor and M. Imai. ACM Transactions on Design Automation of Embedded Systems (TODAES), 12(4):(Article no. 41), Sep 2007. [BIB]
• Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
  Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal and Geert Deconinck. IEEE Transactions on Computers, 54(6):672-683, June 2005. [BIB]
• Instruction Buffering Exploration for Low Energy Embedded Processors.
  Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal and Francky Catthoor. Journal of Embedded Computing, 1(3), 2004. [BIB]
• Matador: an Exploration Environment for Systems-Design.
  Pol Marchal, Murali Jayapala, Samuel de Souza, Peng Yang, Francky Catthoor and Geert Deconinck. Journal on Circuits Systems and Computers special issue on Power Simulation and Estimation in VLSI Circuits, 11(5):503-536, October 2002. [BIB] [ps]

Book/Book Chapter

• Ultra Low-Power Domain Speciific Instruction Set Processors.
  Francky Catthoor, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou and Javed Absar, Springer, (In Preparation). [BIB]
• Roadmaps on Selected topics in Embedded Systems Design from the ARTIST project.
  Geert Deconinck, Murali Jayapala and Tom Vander Aa, Mar 2005. [BIB]
• Low Energy Instruction Memory Organization for Embedded Processors.
  Jayapala, Murali. PhD thesis, KULeuven, {ESAT/ELECTA}, 2005. [BIB]

Conference/Workshop Papers

• Compilation Technique for Loop Overhead Minimization.
  Nikolaos Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor and Dimitrios Soudris. In 12th EuroMicro Conference on Digital System Design Architectures Tools and Methods, Aug 2009. [BIB]
• Systematic Architecture Exploration based on Optimistic Cycle Estimation for Low Energy Embedded Processors.
  Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi and Masaharu Imai. In The 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 449-454, Jan 2009. [BIB]
• Operation Shuffling over Cycle Boundaries for Low Energy L0 Clustering.
  Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor and Masaharu Imai. In 19th IEEE International Conference Application-specific Systems Architectures and Processors (ASAP) , Jul 2008. [BIB]
• Cost-aware Strength Reduction for Constant Multiplication in VLIW Processors.
  Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor and Diederik Verkest. In Proc of 6th Workshop on Optimizations for DSP and Embedded Systems (ODES) together with CGO2008), Jan 2008. [BIB]
• COFFEE: COmpiler Framework For Energy-aware Expoloration.
  P Raghavan, A Lambrechts, J Absar, and M Jayapala and F Catthoor. In Proc of HiPEAC, Jan 2008. [BIB]
• Energy-Aware Interconnect Exploration for a Coarse Grained Reconfigurable Processor.
  Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor and Diederik Verkest. In Proc of VLSIDesign, Jan 2008. [BIB]
• Locality Optimization in Wireless Applications.
  J Absar, M Li, A Lambrechts, P Raghavan, M Jayapala, A Vandecappelle and F Catthoor. In Proc of CODES+ISSS, Oct 2007. [BIB]
• Semi Custom Design: A Case Study on SIMD Shufflers.
  Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor and Diederik Verkest. In Proc of PATMOS, Sep 2007. [BIB]
• Impact of ILP-improving Code Transformations on Loop Buffer Energy.
  Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor and Geert Deconinck. In Proc of INTERACT Workshop (in conjuction with HPCA), Feb 2007. [BIB]
• Enabling WordWidth Aware Energy and Performance Optimizations for Embedded Processors.
  Andy Lambrechts, Praveen Raghavan, David Novo, Estela Rey Ramos, Murali Jayapala, Francky Catthoor and Diederik Verkest . In Workshop on Optimizations for DSP and Embedded Systems, Mar 2007. [BIB]
• A Customized Cross-Bar for Data-Shuffling in Domain Specific SIMD Processors.
  P.Raghavan, S.Munaga, E.Rey Ramos, A.Lambrechts, M.Jayapala, F.Catthoor and D.Verkest. In Proc of Architecture and Computing Systems (ARCS), 2007. [BIB]
• Architectures and Circuits for Software Defined Radios: scaling and scalability for low cost and low energy.
  L. Van der Perre, B. Bougard, J. Craninckx, W. Dehaene, L. Hollevoet, M. Jayapala, P. Marchal, M. Miranda, P. Raghavan, T. Schuster, P. Wambacq, F. Catthoor and P. Vanbekbergen. In IEEE International Solid-State Circuits Conference (ISSCC), 2007. [BIB]
• Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors.
  P.Raghavan, A.Lambrechts, M.Jayapala, F.Catthoor, D.Verkest and H. Corporaal. In "DATE '07: Proceedings of the conference on Design, 2007. [BIB]
• Instruction Transfer And Storage Exploration for Low Energy VLIWs.
  "Vander Aa. In Proc. of IEEE 2006 Workshop on Signal Processing Systems (SiPS 2006), pages 313 - 318, Banff AB Canada 01-03 Oct 2006, 10 2006. [BIB]
• Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors.
  P.Raghavan, A.Lambrechts, M.Jayapala, F.Catthoor and D.Verkest. In "DATE '06: Proceedings of the conference on Design, Washington, DC, USA, 2006. [BIB] [pdf]
• Efficient Architecture Exploration of a Clustered Loop Buffer.
  "Vander Aa. In Proc. of International workshop on Optimizations for DSPs and Embedded Systems 2006 (ODES2006), New York USA 26-29 March 2006. [BIB]
• "Empirical power model for register files" P.Raghavan, A.Lambrechts, M.Jayapala, F.Catthoor, and D.Verkest, in In Workshop on Media and Streaming Processors (with MICRO-38), November 2005
• "Operation shuffling for low energy l0 cluster generation on heterogeneous VLIW processors" Y.Kobayashi, M.Jayapala, P.Raghavan, F.Catthoor, and M.Imai, in IEEE Workshop on Embedded Systems for Realtime Multimedia (ESTIMEDIA), September 2005.
• Energy-Aware Interconnect-Exploration of Coarse Grained Reconfigurable Processors.
  Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Diederik Verkest and Francky Catthoor. In IEEE Workshop on Application Specific Processors, September 2005. [BIB]
• Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
  Andy Lambrecths, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Coporaal, Fr{\'e}d{\'e}ric Robert and Jordi Carrabina. In "Proc of IEEE 16th International Conference on Application-specific Systems, July 2005. [BIB]
• Design Style Case Study for Compute Nodes of a Heterogenenous NoC Platform.
  Andy Lambrecths, Tom Vander Aa, Murali Jayapala, Antony Leroy, Guillermo Talavera, Adriana Shickova, Francisco Barat, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Coporaal, F. Robert and J. C. Bordoll. In 25th IEEE Real-Time Systems Symposium (RTSS), December 2004. [BIB] [pdf]
• L0 Cluster Synthesis and Operation Shuffling.
  Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Coporaal and Geert Deconinck. In "Proc of 14th International Workshop on Power And Timing Modeling, September 2004. [BIB] [pdf]
• Instruction Buffering Exploration for Low Energy VLIWs with Instruction Clusters.
  Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor and Henk Corporaal. In Proc. of the Asian Pacific Design and Automation Conference 2004 (ASPDAC'2004), "Yokohama, January 2004. [BIB] [pdf]
• Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
  Francisco Barat, Murali Jayapala, Tom Vander Aa, Geert Deconinck, Rudy Lauwereins and Henk Corporaal. In Proc of 13th International Conference on Field Programmable Logic and Applications (FPL), September 2003. [BIB]
• Instruction Buffering Exploration for Low Energy Embedded Processors.
  Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal and Francky Catthoor. In "Proc of 13th International Workshop on Power And Timing Modeling, September 2003. [BIB] [pdf]
• Clustered L0 Buffer Organization for Low Energy Embedded Processors.
  Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Geert Deconinck and Henk Corporaal. In "Proc of 1st Workshop on Application Specific Processors (WASP), November 2002. [BIB] [pdf]
• A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
  Murali Jayapala, Francisco Barat, Pieter OpDeBeeck, Francky Catthoor, Geert Deconinck and Henk Corporaal. In Proc of 12th International Workshop on Power And Timing Modeling Optimization and Simulation (PATMOS) , September 2002. [BIB] [pdf]
• Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.
  Francisco Barat, Murali Jayapala, Pieter OpDeBeeck and Geert Deconinck. In Proc of VLSI Design together with ASPDAC, January 2002. [BIB] [pdf]
• Low Energy Clustered Instruction Fetch and Split A Loop Cache Architecture For Long instruction Word Processors.
  Murali Jayapala, Francisco Barat, Pieter OpDeBeeck, Francky Catthoor and Rudy Lauwereins. In Proc of the workshop on Compilers and Operating Systems for Low Power (COLP), September 2001. [BIB] [pdf]
• Inner Loop Code Generation for Coarse-Grained Reconfigurable Instruction Set Processors.
  Francisco Barat, Murali Jayapala, Pieter OpDeBeeck and Rudy Lauwereins. In Proc of International Workshop on Advanced Parallel Processing Techniques (APPT), September 2001. [BIB] [pdf]
• CRISP: A Template for Reconfigurable Instruction Set Processors.
  Pieter OpDeBeeck, Francisco Barat, Murali Jayapala and Rudy Lauwereins. In Proc of International conference on Field Programmable Logic (FPL), August 2001. [BIB] [pdf]
• Reconfigurable Instruction Set Processors: An Implementation Platform for Interactive Multimedia Applications.
  Francisco Barat, Murali Jayapala, Pieter OpDeBeeck and Geert Deconinck. In Proc of Asilomar Conference, November 2001. [BIB] [pdf]